Transmitting data from one component of a computer system to a second component of a computer system is typically an important aspect in the execution of tasks. If the data needed by the first component of a system resides on the second component and is of a substantial size, the system resources, such as the Central Processing Unit (CPU), are “tied up” (i.e., unavailable) for the period of time required to move the data. The unavailable time is often burdensome to the execution of tasks and can sometimes be critical to the performance of the computer system.
To transfer data efficiently, computer systems typically employ a Direct Memory Access (DMA) controller to transfer data from a source location to a target location without the intervention of the CPU. Further, a computer system may have multiple DMA controllers that each operate independently to transfer data between multiple I/O devices and memory. The multiple DMA controllers generally transfer blocks of data having a specific size and at a particular transfer rate.
However, the multiple DMA controllers can still generally be inefficient when transferring blocks of data at a particular transfer rate. First, transferring data of a particular size between one I/O device and memory at a particular transfer rate can be inefficient in that the data can have a substantial size and consequently slow the operations of the computer system.
Additionally, one DMA controller transfers data having the specific size between a particular block of memory and an I/O device. Moreover, when the data block has a size that is large enough to require multiple DMA transactions, the time to complete the transaction is increased.